This invention relates to semiconductor memory, in particular to a redundant circuit in a memory cell array to repair a defective cell.
In a memory cell array, there are a large number of memory cells. As demand and technology progress, the memory size and chip size also increase. With increased chip size, the likelihood of having a defective cell in the chip becomes greater. While there has been constant effort to improve the yield of production, another remedy is to use circuit approach.
When one of the cells is defective, the memory chip cannot function properly. It is customary to incorporate redundant word line(s) in the memory chip to replace the line where there is a defective cell such as that described in U.S. Pat. No. 4,571,707. On such redundant circuit block diagram is shown in FIG. 1. When the memory chip receives data to be stored in normal operating condition, the X address signal XA picks one out of n-inputs to feed an X address predecoder 32X to select one of 2.sup.n word lines. Meanwhile the Y address signal YA selects one of m-addresses of a Y-predecoder 31Y to feed a Y address decoder 32Y which selects one of 2.sup.m column. With coincident addressing, a 2.sup.n *2.sup.m addressable memory matrix is obtained. The input data is stored in the one addressed memory cell out of the 2.sup.n *2.sup.m memory cells matrix.
If there is defective memory cell, the X-control circuit 33X activates an X-repair circuit 34X or the Y-control circuit 33Y activates a Y-repair circuit 34Y. For example, when a memory chip is found by factory testing to have a defective memory cell at location [1,1] . . . [1,2] word line, the location is recorded in the X-control circuit 33X which is activated at the appropriate time to remedy the defective word line WL[1]. When thee new address signal arrives and if the address coincides with that of the word line WL[1] (such as 0001 etc), the X control circuit 33X produces an enable signal Fuen X (function enable) to activate the X-repair circuit 34X. The Fuen X signal feeds the X-repair circuit 34X to generate a repair signal RX. The RX signal deactivates the original X address in the decoder 32X so that the normal word line in 32X cannot be activated, but activates a spare word line in the memory matrix 3 to replace the original defective word line. Thus the repair function is accomplished.
FIG. 2 shows a circuit diagram of a conventional repair circuit (such as 34X). A number of n-type MOSFETs (NMOS) 104-107 are connected in parallel each through a fuse F11, F12, F13, F14 respectively between a ground and a common node A, which is connected to the common drain of a CMOS inverter having a PMOS 102 and an NMOS 122. The gates of the NMOS 104-107 are separately connected to the input addresses of the predecoder (such as 31X), e.g. A[0], A[0]B, A[1], A[1]B, A[2], A[2]B, A[3], A[3]B for 4 input address. The common gate of the CMOS inverter 102/122 is connected to the output of inverter 101, which receives the FuenX enable signal from the X control circuit 33X. The inverter 101 also drives the common gate of another CMOS inverter comprising PMOS 103 and NMOS 123. The common drain the 103 and 123 drives another common node B. Between node B and the ground are connected in parallel another set of NMOS 108-111 each in series with a fuse F15, F16, F17,F18 respectively. The nodes A and B are connected to a NAND gate 112 which feeds inverter 113.
In operation, the fuses F11-F18 can be rendered non-conductive (open) either electrically or mechanically. When the control circuit feeds a high ("1") Fuen enable signal to inverter 101, PMOS 102 and 103 are turned on. If none of the series NMOS and fuse paths of NMOS between node A and ground is conducting, the node A is pulled up to "1" level. Similarly, the same is true for node B. When, the output nodes A and B are set in high logic level "1", a high RX signal is generated.
For example, if the address 1111 in the memory matrix is defective, the fuses F11, F13, F15, F17 are made nonconductive and the fuses F12, F14, F16, F18 are made conductive. Then, when Fuen enable signal is fed to inverter 101 and the addresses of the predecoder is 1111 (i.e. A[0]=1, A[0]B=0; A[1]=1, A[1]B=0; A[2]=1, A[2]N=0; A[3]=1, A[3]B=0), the NMOS 104, 106, 108, 110 are turned on but their respective series fuses are preset to be broken. On the other hand, the NMOS 105, 107, 109, 111 are not turned on, while their respective series fuses are not broken. Thus none of the NMOS 104-111 are conducting, and both the node A and B are pulled up to logic "1" level. The high logic level "1" of node A and node B renders the output of the NAND 112 to be low and the output RX of the inverter 113 to be high.
However, when the address to the repair circuit shown in FIG.2 is other than 1,1,1,1 at least one of the series NMOS and fuse is conducting. The conducting current consumes power. When the memory is large, the power consumption can be significant.